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http://hdl.handle.net/11320/9223
Tytuł: | Stability of the 7-3 Compressor Circuit for Wallace Tree. Part I |
Autorzy: | Wasaki, Katsumi |
Słowa kluczowe: | arithmetic processor high order compressor high-speed multiplier Wallace tree logic circuit stability |
Data wydania: | 2020 |
Data dodania: | 10-cze-2020 |
Wydawca: | DeGruyter Open |
Źródło: | Formalized Mathematics, Volume 28, Issue 1, Pages 65-77 |
Abstrakt: | To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 7-3 Compressor (STC) Circuit [6] for Wallace Tree [11], to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [10]. We define the circuit structure of the tree constructions of the Generalized Full Adder Circuits (GFAs). We then successfully prove its circuit stability of the calculation outputs after four and six steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability, and to implement the applications of the reliable logic synthesizer and hardware compiler [5]. |
Afiliacja: | Shinshu University, Nagano, Japan |
Sponsorzy: | This work has been partially supported by the JSPS KAKENHI Grant Number 19K11821, Japan. |
URI: | http://hdl.handle.net/11320/9223 |
DOI: | 10.2478/forma-2020-0005 |
ISSN: | 1426-2630 |
e-ISSN: | 1898-9934 |
metadata.dc.identifier.orcid: | 0000-0002-4719-459X |
Typ Dokumentu: | Article |
metadata.dc.rights.uri: | http://creativecommons.org/licenses/by-sa/3.0/pl/ |
Występuje w kolekcji(ach): | Formalized Mathematics, 2020, Volume 28, Issue 1 |
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forma_2020_28_01_0005.pdf | 254,66 kB | Adobe PDF | Otwórz |
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