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http://hdl.handle.net/11320/9223Pełny rekord metadanych
| Pole DC | Wartość | Język |
|---|---|---|
| dc.contributor.author | Wasaki, Katsumi | - |
| dc.date.accessioned | 2020-06-10T10:22:18Z | - |
| dc.date.available | 2020-06-10T10:22:18Z | - |
| dc.date.issued | 2020 | - |
| dc.identifier.citation | Formalized Mathematics, Volume 28, Issue 1, Pages 65-77 | pl |
| dc.identifier.issn | 1426-2630 | - |
| dc.identifier.uri | http://hdl.handle.net/11320/9223 | - |
| dc.description.abstract | To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 7-3 Compressor (STC) Circuit [6] for Wallace Tree [11], to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [10]. We define the circuit structure of the tree constructions of the Generalized Full Adder Circuits (GFAs). We then successfully prove its circuit stability of the calculation outputs after four and six steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability, and to implement the applications of the reliable logic synthesizer and hardware compiler [5]. | pl |
| dc.description.sponsorship | This work has been partially supported by the JSPS KAKENHI Grant Number 19K11821, Japan. | pl |
| dc.language.iso | en | pl |
| dc.publisher | DeGruyter Open | pl |
| dc.rights | Uznanie autorstwa-Na tych samych warunkach 3.0 Polska | * |
| dc.rights.uri | http://creativecommons.org/licenses/by-sa/3.0/pl/ | * |
| dc.subject | arithmetic processor | pl |
| dc.subject | high order compressor | pl |
| dc.subject | high-speed multiplier | pl |
| dc.subject | Wallace tree | pl |
| dc.subject | logic circuit stability | pl |
| dc.title | Stability of the 7-3 Compressor Circuit for Wallace Tree. Part I | pl |
| dc.type | Article | pl |
| dc.identifier.doi | 10.2478/forma-2020-0005 | - |
| dc.description.Affiliation | Shinshu University, Nagano, Japan | pl |
| dc.description.references | Grzegorz Bancerek and Yatsuka Nakamura. Full adder circuit. Part I. Formalized Mathematics, 5(3):367–380, 1996. | pl |
| dc.description.references | Grzegorz Bancerek, Czesław Bylinski, Adam Grabowski, Artur Korniłowicz, Roman Matuszewski, Adam Naumowicz, Karol Pak, and Josef Urban. Mizar: State-of-the-art and beyond. In Manfred Kerber, Jacques Carette, Cezary Kaliszyk, Florian Rabe, and Volker Sorge, editors, Intelligent Computer Mathematics, volume 9150 of Lecture Notes in Computer Science, pages 261–279. Springer International Publishing, 2015. ISBN 978-3-319-20614-1. doi:10.1007/978-3-319-20615-8_17. | pl |
| dc.description.references | Grzegorz Bancerek, Czesław Bylinski, Adam Grabowski, Artur Korniłowicz, Roman Matuszewski, Adam Naumowicz, and Karol Pak. The role of the Mizar Mathematical Library for interactive proof development in Mizar. Journal of Automated Reasoning, 61(1):9–32, 2018. doi:10.1007/s10817-017-9440-6. | pl |
| dc.description.references | Adam Grabowski, Artur Korniłowicz, and Adam Naumowicz. Four decades of Mizar. Journal of Automated Reasoning, 55(3):191–198, 2015. doi:10.1007/s10817-015-9345-1. | pl |
| dc.description.references | Naoki Iwasaki and Katsumi Wasaki. A meta hardware description language melasy for model-checking systems. In Proceedings 5th International Conference on Information Technology: New Generations (ITNG 2008), pages 273–278, 2008. doi:10.1109/ITNG.2008.135. | pl |
| dc.description.references | Mayur Mehta, Vijay Parmar, and Earl Swartzlander. High-speed multiplier design using multi-input counter and compressor circuits. In Proceedings 10th IEEE Symposium on Computer Arithmetic, pages 43–50, June 1991. doi:10.1109/ARITH.1991.145532. | pl |
| dc.description.references | Yatsuka Nakamura and Grzegorz Bancerek. Combining of circuits. Formalized Mathematics, 5(2):283–295, 1996. | pl |
| dc.description.references | Yatsuka Nakamura, Piotr Rudnicki, Andrzej Trybulec, and Pauline N. Kawamoto. Introduction to circuits, I. Formalized Mathematics, 5(2):227–232, 1996. | pl |
| dc.description.references | Yatsuka Nakamura, Piotr Rudnicki, Andrzej Trybulec, and Pauline N. Kawamoto. Introduction to circuits, II. Formalized Mathematics, 5(2):273–278, 1996. | pl |
| dc.description.references | Jean Vuillemin. A very fast multiplication algorithm for VLSI implementation. Integration, 1(1):39–52, 1983. doi:10.1016/0167-9260(83)90005-6. | pl |
| dc.description.references | Christopher Stewart Wallace. A suggestion for a fast multiplier. IEEE Transactions on Electronic Computers, EC-13(1):14–17, 1964. doi:10.1109/PGEC.1964.263830. | pl |
| dc.description.references | Katsumi Wasaki. Stability of the 4-2 binary addition circuit cells. Part I. Formalized Mathematics, 16(4):377–387, 2008. doi:10.2478/v10037-008-0046-7. | pl |
| dc.description.references | Katsumi Wasaki and Pauline N. Kawamoto. 2’s complement circuit. Formalized Mathematics, 6(2):189–197, 1997. | pl |
| dc.description.references | Shin’nosuke Yamaguchi, Katsumi Wasaki, and Nobuhiro Shimoi. Generalized full adder circuits (GFAs). Part I. Formalized Mathematics, 13(4):549–571, 2005. | pl |
| dc.identifier.eissn | 1898-9934 | - |
| dc.description.firstpage | 65 | pl |
| dc.description.lastpage | 77 | pl |
| dc.identifier.citation2 | Formalized Mathematics | pl |
| dc.identifier.orcid | 0000-0002-4719-459X | - |
| Występuje w kolekcji(ach): | Formalized Mathematics, 2020, Volume 28, Issue 1 | |
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